The layout design of integrated circuit is an image of a three-dimensional arrangement, expressed in any way, of the elements contained in the integrated circuit, and the connections between all or some of the elements, or of a three-dimensional arrangement designed to be used in the manufacture of the integrated circuit, with at least one element being an active element.
The essential characteristics of the the integrated circuit, such as dimensions, energy consumption, operating speed, etc. depend on the layout of the elements and connections.
Legal protection is granted to a layout design of integrated circuit that is original and has not been used for commercial purposes in any part of the world for more than two years prior to the registration of the layout design of integrated circuit in the register. The layout design of integrated circuit is original if it is the result of the creative activity of its creator and is not common for experts in the creation and production of a layout design of integrated circuit at the time of creation.
The legal protection does not extend to the layout design of integrated circuit or microcircuit-making technology, nor to the information stored in them. The legal protection of the layout design of integrated circuit will be granted for a period of ten years and will expire ten calendar years after the last calendar day of the beginning of the legal protection.
According to the Layout-Designs of Integrated Circuits Protection Act, an application or registration system is applied for the registration of layout design of integrated circuit.
The right to apply for the layout design of integrated circuit and to become the owner of the layout design of integrated circuit belongs to the author or to the person to whom the author has transferred the right to register the layout design of integrated circuit. The employer or the contractor will have the right to apply for the registration of the layout design of integrated circuit created in the performance of duties or contractual obligations and to become the owner of the layout design of integrated circuit, unless provided otherwise in the assignment or contract.
Matters relating to registration may be handled through patent attorneys or done independently. If the residence or seat of the applicant is outside Estonia, the activities following the filing of the application for registration must be carried out by the patent attorney. An application for registration of a layout design of integrated circuit may contain only one layout design of integrated circuit.
The application for registration must contain of the following documents:
- An application for registration of the layout design of integrated circuit, which must be submitted to the Estonian Patent Office.
- Documents identifying the layout design of integrated circuit, which must give a complete and accurate picture of the layout design of integrated circuit.
- A document certifying payment of the state fee.
- Authorization letter if the applicants have a joint representative.
The registration application documents must be filed in Estonian.
The application for registration must be filed directly by the applicant or their representative or by post at the reception of the Estonian Patent Office.
The Estonian Patent Office will verify the existence of registration application documents provided for by law and their compliance with the established formal requirements, as well as compliance with the deadlines for submission of documents, correctness of paid state fees and the right to represent the applicant in proceedings with the Estonian Patent Office. The Estonian Patent Office will not verify the applicant's right to submit the application, the accuracy of the facts presented in the application or the originality of the layout design of integrated circuit.
If the application for registration meets the requirements, the Estonian Patent Office takes a decision to register the layout design of integrated circuit and will inform the applicant in writing.
The state fees should be payed to the bank accounts of the Ministry of Finance.
- SEB Pank EE571010220229377229 (SWIFT: EEUHEE2X)
- Swedbank EE062200221059223099 (SWIFT: HABAEE2X)
- LHV Pank EE567700771003819792 (BIC/SWIFT: LHVBEE22)
- Luminor Bank EE221700017003510302 (SWIFT: RIKOEE22)
When paying the state fees, a unique reference number provided by the Estonian Patent Office should be used. It will be provided to you after you have filed the application for the required proceeding.
If you have paid the state fees before the Patent Office has provided to you the unique reference number, the reference number field should be left blank and the data concerning the payment should be submitted to the Patent Office at [email protected].
| Description | State fee (€) |
|---|---|
|
For filing of an application for registration of a layout design of integrated circuit |
105 |
|
For extension of the term for elimination of deficiencies in an application for registration of a layout design of an integrated circuit, and for provision of explanations |
32 |
|
Restoration of the examination of the registration application of a layout design of integrated circuit |
32 |
|
For filing of an application for amendment of data on the applicant upon transfer of an application for registration of a layout design of integrated circuit |
32 |
|
For filing of an application for a registration entry of the transfer or licence of layout design of an integrated circuit |
32 |
Last updated: 09.01.2025